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LTC1473L 1 the ltc ? 1473l provides reliable and efficient switching between two dc power sources. this device drives two external sets of back-to-back n-channel mosfet switches to route power to the input of a low voltage system. an internal boost regulator provides the voltage to fully en- hance the logic-level n-channel mosfet switches while an internal undervoltage lock-out circuit keeps the system alive down to 2.8v. the LTC1473L senses current to limit inrush between the batteries and the system supply capacitor during switch- over transitions or during fault conditions. a user-pro- grammable timer monitors the time the mosfet switches are in current limit and latches them off when the pro- grammed time is exceeded. a unique 2-diode logic mode ensures system start-up regardless of which input receives power first. n portable computers n portable instruments n fault tolerant computers n battery-backup systems n 3.3v/5v power management , ltc and lt are registered trademarks of linear technology corporation. n power path management for systems with multiple dc sources n switches and isolates sources from 3.3v to 10v n all n-channel switching to reduce power losses and system cost n built-in step-up regulator for n-channel gate drive n capacitor inrush and short-circuit current limited n user-programmable timer prevents overdissipation during current limiting n undervoltage lockout prevents operation with low inputs n small footprint: 16-pin narrow ssop dual low voltage powerpath tm switch driver powerpath is a trademark of linear technology corporation. 3.3v to 4-cell nimh backup switch in1 in2 diode timer v + v gg sw gnd 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 ga1 sab1 gb1 sense + sense ga2 sab2 gb2 LTC1473L c out r sense 0.04 w 1 m f 1mh* si9926dy bat54c 1473 ta01 dcin 3.3v v bat1 4 nimh logic driven 3.3v or v bat1 c timer 2000pf si9926dy 1 m f + * coilcraft 1812ls-105xkbc applicatio s u features typical applicatio u descriptio u
LTC1473L 2 absolute axi u rati gs w ww u package/order i for atio uu w (note 1) electrical characteristics order part number LTC1473Lcgn t jmax = 125 c, q ja = 150 c/ w consult factory for military and industrial grade parts. sense + , sense C , v + .................................. C 0.3 to 10v ga1, gb1, ga2, gb2 ................................... C 0.3 to 20v sab1, sab2 ................................................. C 0.3 to 10v sw, v gg ...................................................... C 0.3 to 20v in1, in2, diode ...........................................C 0.3v to 7v junction temperature (note 2) ............................. 125 c operating temperature range ..................... 0 c to 70 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c gn part marking 1473l symbol parameter conditions min typ max units v + supply operating range 2.8 9 v i s supply current v in1 = v diode = 5v, v in2 = 0v, v sense + = v sense C = 5v l 100 200 m a v gs v gs gate supply voltage v gs = v gg C v + , 2.8v v + 10v (note 3) l 7.5 8.5 9.5 v v + uvlo v + undervoltage lockout threshold v + ramping down l 2.3 2.5 2.8 v v + uvlohys v + undervoltage lockout hysteresis 70 mv v hidigin digital input logic high (note 4) l 2 0.9 v v lodigin digital input logic low (note 4) l 0.6 0.4 v i in input current v in1 = v in2 = v diode = 5v 1 m a v gs(on) gate-to-source on voltage i ga1 = i ga2 = i gb1 = i gb2 = C 1 m a, v sab1 = v sab2 = 5v l 4.5 5.6 7.0 v v gs(off) gate-to-source off voltage i ga1 = i ga2 = i gb1 = i gb2 = 100 m a, v sab1 = v sab2 = 5v l 0 0.4 v i bsense + sense + input bias current v sense + = v sense C = 10v (note 3) l 24.510 m a v sense + = v sense C = 0v (note 5) l C 300 C 175 C 75 m a i bsense C sense C input bias current v sense + = v sense C = 10v (note 3) l 24.510 m a v sense + = v sense C = 0v (note 5) l C 300 C 175 C 75 m a v sense inrush current limit sense voltage v sense C = 10v (v sense + C v sense C ) (note 3) 0.15 0.20 0.25 v v sense C = 0v (v sense + C v sense C ) 0.10 0.20 0.30 v i pdsab sab1, sab2 pull-down current v in1 = v in2 = v diode = 0.4v, v + = 10v (note 3) 5 20 35 m a v in1 = v in2 = 0.4v, v diode = 2v 30 140 300 m a i timer timer source current v in1 = 0.4v, v in2 = v diode = 2v, v timer = 0v, l 369 m a v sense + C v sense C = 300mv v timer timer latch threshold voltage v in1 = 0.4v, v in2 = v diode = 2v l 1.05 1.16 1.25 v t on gate drive rise time c gs = 1000pf, v sab1 = v sab2 = 0v (note 6) 33 m s t off gate drive fall time c gs = 1000pf, v sab1 = v sab2 = 5v (note 6) 2 m s t d1 gate drive turn-on delay c gs = 1000pf, v sab1 = v sab2 = 0v (note 6) 22 m s t d2 gate drive turn-off delay c gs = 1000pf, v sab1 = v sab2 = 5v (note 6) 1 m s f ovgg v gs regulator operating frequency 30 khz the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. test circuit, v + = 5v, unless otherwise specified. top view gn package 16-lead narrow plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 in1 in2 diode timer v + v gg sw gnd ga1 sab1 gb1 sense + sense ga2 sab2 gb2
LTC1473L 3 note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d )(150 c/w) note 3: some tests are performed under more stringent conditions to ensure reliable operation over the entire supply voltage range. electrical characteristics note 4: digital inputs include: in1, in2 and diode. note 5: i s increases by the same amount as i bsense + + i bsense C when their common mode falls below 5v. note 6: gate turn-on and turn-off times are measured with no inrush current limiting, i.e., v sense = 0v. gate rise times are measured from 1v to 4.5v and fall times are measured from 4.5v to 1v. delay times are measured from the input transition to when the gate voltage has risen or fallen to 3v. results are not tested, but guaranteed by design. dc supply current vs supply voltage v gs gate-to-source on voltage vs temperature dc supply current vs v sense v sense common mode (v) 0 supply current ( a) 1473 g03 567 10 1234 89 400 350 300 250 200 150 100 50 0 v + = 5v v diode = v in1 = 5v v in2 = 0v v sense + ?v sense = 0v v gs gate supply voltage vs temperature temperature ( c) 604020 20406080 0 5.1 v gs gate-to-source on voltage (v) 5.2 5.4 5.5 5.6 6.0 1473 g04 5.3 100 5.7 5.8 5.9 v + = v sab = 10v supply voltage (v) 0 supply current ( m a) 50 150 10 1473 g01 0 2 456789 13 250 100 200 v diode = v in1 = 5v v in2 = 0v v diode = 5v v in1 = v in2 = 0v v sense + = v sense = v + temperature ( c) ?0 ?0 8.1 v gs gate supply voltage (v) 8.2 8.4 8.5 8.6 0 9.0 1473 g06 8.3 20 20406080100 8.7 8.8 8.9 v + = 5v v gs = v gg ?v + dc supply current vs temperature undervoltage lockout threshold (v + ) vs temperature temperature ( c) ?0 50 supply current ( m a) 60 80 90 100 0 140 1473 g02 70 25 25 50 75 100 110 120 130 v + = 5v v diode = v in1 = 5v v in2 = 0v temperature ( c) ?0 2.25 undervoltage lockout threshold (v) 2.30 2.40 2.45 2.50 2.75 2.60 ?0 20 40 1473 g05 2.35 2.65 2.70 2.55 ?0 0 60 80 100 start-up threshold shutdown threshold typical perfor a ce characteristics uw
LTC1473L 4 typical perfor a ce characteristics uw turn-off delay and gate fall time vs temperature temperature ( c) ?0 ?0 0.4 turn-off delay and gate fall time ( m s) 0.6 1.0 1.2 1.4 0 2.2 1473 g07 0.8 20 20406080100 1.6 1.8 2.0 gate fall time v + = 5v c load = 1000pf v sab = 5v turn-off delay rise and fall time vs gate capacitive loading gate capacitive loading (pf) 10 20 rise and fall time ( m s) 30 40 100 1000 10000 1473 g08 10 5 25 35 15 0 rise time v sab = 0v fall time v sab = 5v turn-on delay and gate rise time vs temperature temperature ( c) ?0 0 turn-on delay and gate rise time ( m s) 5 15 20 25 0 45 1473 g08 10 40 20 20 40 60 80 100 30 35 40 gate rise time v + = 5v c load = 1000pf v sab = 0v turn-on delay sense pin source current (i bsense ) vs v sense v sense (v) sense pin current ( a) 1473 g13 v + = 5v v diode = v in1 = 5v v in2 = 0v v sense + ?v sense = 0v 0 300 250 200 150 100 50 0 ?0 123456789 10 timer source current vs temperature temperature ( c) ?0 4.0 timer source current ( m a) 4.5 5.5 6.0 6.5 0 8.5 1473 g12 5.0 25 25 50 75 100 125 7.0 7.5 8.0 v + = 5v timer = 0v temperature ( c) ?0 1.10 timer latch threshold voltage (v) 1.12 1.16 1.18 1.20 0 1.28 1473 g11 1.14 25 25 50 75 100 125 1.22 1.24 1.26 v + = 5v timer latch threshold voltage vs temperature logic input threshold voltage vs temperature temperature ( c) ?0 0 input threshold voltage (v) 0.2 0.6 0.8 1.0 2.0 1.4 ?0 20 40 1473 g10 0.4 1.6 1.8 1.2 ?0 0 60 80 100 v + = 10v v + = 2.8v
LTC1473L 5 pi fu ctio s uuu sw (pin 7): open drain of an internal n-channel mosfet switch. this pin drives the bottom of the v gg switching regulator inductor which is connected between this pin and the v + pin. gnd (pin 8): ground. gb2, ga2 (pins 9, 11): switch gate drivers. ga2 and gb2 drive the gates of the second back-to-back external n-channel switches. sab2 (pin 10): source return. the sab2 pin is connected to the sources of sw a2 and sw b2. a small pull-down current source returns this node to 0v when the switches are turned off. sense C (pin 12): inrush current input. this pin should be connected directly to the bottom (output side) of the low valued resistor in series with the two input power selector switch pairs, sw a1/b1 and sw a2/b2, for detecting and controlling the inrush current into and out of the power supply sources and the output capacitor. sense + (pin 13): inrush current input. this pin should be connected directly to the top (switch side) of the low valued resistor in series with the two input power selector switch pairs, sw a1/b1 and sw a2/b2, for detecting and controlling the inrush current into and out of the power supply sources and the output capacitor. current limit is invoked when (v sense + C v sense C ) exceeds 0.2v. in1 (pin 1): logic input of gate drivers ga1 and gb1. in1 is disabled when in2 is high or diode is low. during 2-diode mode, asserting in1 disables the fault timer function. in2 (pin 2): logic input of gate drivers ga2 and gb2. in2 is disabled when in1 is high or diode is low. during 2-diode mode, asserting in2 disables the fault timer function. diode (pin 3): 2-diode mode logic input. diode over- rides in1 and in2 by forcing the two back-to-back external n-channel mosfet switches to mimic two di- odes. timer (pin 4): fault timer. a capacitor connected from this pin to gnd programs the time the mosfet switches are allowed to be in current limit. to disable this function, pin 4 can be grounded. v + (pin 5): power supply. bypass this pin with at least a 1 m f capacitor. v gg (pin 6): gate driver supply. this high voltage supply is intended only for driving the internal micropower gate drive circuitry. do not load this pin with any external circuitry . bypass this pin with at least 1 m f. pin function table nominal (v) absolute max (v) pin name description min typ max min max 1 in1 logic input of gate drivers ga1 and gb1 0.4 1 2 C 0.3 7 2 in2 logic input of gate drivers ga2 and gb2 0.4 1 2 C 0.3 7 3 diode 2-diode mode logic input 0.4 1 2 C 0.3 7 4 timer fault timer programs time in current limit 1.16 C 0.3 5 5v + power supply 2.8 9 C 0.3 10 6v gg gate driver supply 10.2 20 C 0.3 20 7 sw switch node of internal boost switching regulator 0 20 C 0.3 20 8 gnd ground 0 0 0 9 gb2 switch gate driver for switch b2 0 17 C 0.3 20 10 sab2 source return of switch 2 0 10 C 0.3 10 11 ga2 switch gate driver for switch a2 0 17 C 0.3 20 12 sense C inrush current input, low side 0 10 C 0.3 10 13 sense + inrush current input, high side 0 10 C 0.3 10 14 gb1 switch gate driver for switch b1 0 17 C 0.3 20 15 sab1 source return of switch 1 0 10 C 0.3 10 16 ga1 switch gate driver for switch a1 0 17 C 0.3 20
LTC1473L 6 pi fu ctio s uuu fu ctio al diagra uu w gb1, ga1 (pins 14, 16): switch gate drivers. ga1 and gb1 drive the gates of the first back-to-back external n-channel switches. sab1 (pin 15): source return. the sab1 pin is connected to the sources of sw a1 and sw b1. a small pull-down current source returns this node to 0v when the switches are turned off. ga1 sab1 gb1 ga2 sab2 gb2 1473 fd sense + sense in1 in2 diode v + timer v + sw to gate drivers v gg gnd 1.16v v gg switching regulator inrush current sense 900k 6 a latch r s + sw a1/b1 gate drivers sw a2/b2 gate drivers 16 15 14 13 12 11 10 9 8 6 5 4 3 2 1 7
LTC1473L 7 operatio u the LTC1473L is responsible for low-loss switching and isolation for a dual supply system, where during a power backup situation, a battery pack can be connected or disconnected seamlessly. smooth switching between in- put power sources is accomplished with the help of low-loss n-channel switches. they are driven by special gate drive circuitry which limits the inrush current in and out of the battery packs and the system power supply capacitors. all n-channel switching the LTC1473L drives external back-to-back n-channel mosfet switches to direct power from two sources: the primary battery and the secondary battery, or a battery and a dc power supply. (n-channel mosfet switches are more cost effective and provide lower voltage drops than their p-channel counterparts.) gate drive (v gg ) power supply the gate drive for the low-loss n-channel switches is supplied by an internal micropower boost regulator which is regulated at approximately 8.5v above v + , up to 20v maximum. in a dc supply and backup battery system, the LTC1473L v + pin is diode ored through two external schottky diodes connected to the two main power sources, dcin and bat1. thus, v gg is regulated at 8.5v above the higher power source and will provide the overdrive required to fully enhance the mosfet switches. for maximum efficiency the input to the boost regulator inductor is connected to v + as shown in figure 1. c1 provides filtering to the input of the 1mh switched induc- tor, l1, which is housed in a small surface mount package. an internal diode directs the current from the 1mh induc- tor to the v gg output capacitor c2. inrush and short-circuit current limiting the LTC1473L uses an adaptive inrush current limiting scheme to reduce current flowing in and out of the battery and the following systems input capacitor during switch- over transitions. the voltage across a single small valued resistor, r sense , is measured to ascertain the instanta- neous current flowing through either of the two switch pairs, sw a1/b1 and sw a2/b2, during the transitions. figure 2 shows a block diagram of a switch driver pair, sw a1/b1. a bidirectional current sensing and limiting circuit determines when the voltage drop across r sense reaches 200mv. the gate-to-source voltage, v gs , of the appro- priate switch is limited during the transition period until the inrush current subsides. this scheme allows capacitors and mosfet switches of differing sizes and current ratings to be used in the same system without circuit modifications. figure 1. v gg switching regulator figure 2. sw a1/b1 inrush current limiting bat1 dcin v + sw gnd 1473 f01 v gg l1 1mh c1 1 f 25v c2 1 f 25v to gate drivers (8.5v + v + ) LTC1473L v gg switching regulator v sense + v sense ga1 gb1 sab1 sw a1 sw b1 r sense 1473 f02 bat1 + output load c out v gg LTC1473L 6v 6v 200mv threshold sw a/b gate drivers bidirectional inrush current sensing and limiting
LTC1473L 8 after the transition period, the v gs of both mosfets in the selected switch pair rises to approximately 5.6v. the gate drive is set at 5.6v to provide ample overdrive for logic- level mosfet switches without exceeding their maximum v gs rating. in the event of a fault condition, the current limit loop limits the inrush of current into the short. at the instant the mosfet switch is in current limit, i.e., when the voltage drop across r sense is 200mv, a fault timer starts timing. it will continue to time as long as the mosfet switch is in current limit. eventually the preset time will lapse and the mosfet switch will latch off. the latch is reset by dese- lecting the gate drive input. fault time-out is programmed by an external capacitor connected between the timer pin and ground. power path switching concepts power source selection the LTC1473L drives low-loss switches to direct power from either the battery pack or the dc supply during power backup situations. figure 3 is a conceptual block diagram that illustrates the main features of an LTC1473L dual supply power manage- ment system starting with a 4 nimh battery pack and a 5v/ 3.3v dc supply and ending with an uninterrupted output load. switches sw a1/b1 and sw a2/b2 direct power from either the dc supply or the battery to the output load. each of the switches is controlled by a logic compatible input that can interface directly with a digital pin. using tantalum capacitors the inrush (and outrush) current of the load capacitor is limited by the LTC1473L, i.e., the current flowing both in and out of the capacitor during transitions from one input power source to another is limited. in many applications, this inrush current limiting makes it feasible to use lower cost/size tantalum surface mount capacitors in place of more expensive/larger aluminum electrolytics. note: the capacitor manufacturer should be consulted for specific inrush current specifications and limitations and some experimentation may be required to ensure compli- ance with these limitations under all possible operating conditions. back-to-back switch topology the simple spst switches shown in figure 3 actually consist of two back-to-back n-channel switches. these low-loss n-channel switch pairs are housed in 8-pin so or ssop packaging and are available from a number of manufacturers. the back-to-back topology eliminates the problems associated with the inherent body diodes in power mosfet switches and allows each switch pair to block current flow in either direction when the two switches are turned off. figure 3. LTC1473L powerpath conceptual diagram dcin 5v/3.3v bat1 4 nimh inrush current limiting sw a1/b1 sw a2/b2 + 1473 f03 c load LTC1473L applicatio s i for atio wu u u
LTC1473L 9 the back-to-back topology also allows for independent control of each half of the switch pair which facilitates bidirectional inrush current limiting and the so-called 2-diode mode described in the following section. the 2-diode mode under normal operating conditions, both halves of each switch pair are turned on and off simultaneously. for example, when the input power source is switched from bat1 to dcin in figure 4, both gates of switch pair sw a1/b1 are normally turned off and both gates of switch pair sw a2/b2 are turned on. the back-to-back body diodes in switch pair, sw a1/b1, block current flow in or out of the bat1 input connector. in the 2-diode mode, only the first half of each power path switch pair, i.e., sw a1 and sw a2, is turned on; and the second half, i.e., sw b1 and sw b2, is turned off. these two switch pairs now act simply as two diodes connected to the two main input power sources as illustrated in figure 4. the power path diode with the highest input voltage passes current through to the output load to ensure that the output is powered even under start-up or abnormal operating conditions. (an undervoltage lockout circuit defeats this mode when the v + pin drops below 2.5v. the supply to v + comes from the main power sources, dcin and bat1 through two common cathode schottky diodes as shown in figure 1.) the 2-diode mode is asserted by applying an active low to the diode input. component selection n-channel switches the LTC1473L adaptive inrush limiting circuitry permits the use of a wide range of logic-level n-channel mosfet switches. a number of dual low r ds(on) n-channel switches in 8-lead surface mount packages are available that are well suited for LTC1473L applications. the maximum allowable drain-source voltage, v ds(max) , of the two switch pairs, sw a1/b1 and sw a2/b2 must be high enough to withstand the maximum input dc supply voltage. since the dc supply is in the 3.3v to 10v range, 12v mosfet switches will suffice. as a general rule, select the switch with the lowest r ds(on) at the maximum allowable v ds . this will mini- mize the heat dissipated in the switches while increasing the overall system efficiency. higher switch resistances can be tolerated in some systems with lower current requirements, but care should be taken to ensure that the figure 4. LTC1473L powerpath switches in 2-diode mode bat1 dcin sw a2 sw b2 on off r sense 1473 f04 output load + c in sw a1 sw b1 on off LTC1473L applicatio s i for atio wu u u
LTC1473L 10 power dissipated in the switches is never allowed to rise above the manufacturers recommended level. inrush current sense resistor, r sense a small valued sense resistor (current shunt) is used by the two switch pair drivers to measure and limit the inrush or short-circuit current flowing through the conducting switch pair. the inrush current limit should be set at approximately 2 or 3 the maximum required output current. for example, if the maximum current required by the dc/dc converter is 2a, an inrush current limit of 6a is set by selecting a 0.033 w sense resistor, r sense , using the following formula: r sense = (200mv)/i inrush note that the voltage drop across the resistor in this example is only 66mv under normal operating conditions. therefore, the power dissipated in the resistor is ex- tremely small (132mw), and a small 1/4w surface mount resistor can be used in this application (the resistor will tolerate the higher power dissipation during current limit for the duration of the fault time-out). a number of small valued surface mount resistors are available that have been specifically designed for high efficiency current sensing applications. programmable fault timer capacitor, c timer a fault timer capacitor, c timer , is used to program the time duration the mosfet switches are allowed to be in current limit continuously. this feature can be disabled by either grounding the timer pin or asserting diode low and asserting either in1 or in2 high. in the event of a fault condition, the mosfet switch is driven into current limit by the inrush current limit loop. the mosfet switch operating in current limit is in a high dissipation mode and can fail catastrophically if not promptly terminated. the fault time delay is programmed with an external capacitor connected between the timer pin and gnd. at the instant the mosfet switch enters current limit, a 6 m a current source starts charging c timer through the timer pin. when the voltage across c timer reaches 1.16v an internal latch is set and the mosfet switch is turned off. to reset the latch, the logic input of the mosfet gate driver must be deselected. the fault time delay should be programmed as large as possible, at least 3 to 5 the maximum switching transi- tion period, to avoid prematurely tripping the protection circuit. conversely, for the protection circuit to be effec- tive, the fault time delay must be within the safe operating area of the mosfet switches as stated in the manufacturers data sheet. the maximum switching transition period happens during a cold start, when a fully charged battery is connected to an unpowered system. the inrush current charging up the system supply capacitor to the battery voltage determines the switching transition period. the following example illustrates the calculation of c timer. assume the maximum battery voltage is 10v, the system supply capacitor is 100 m f, the inrush current limit is 6a and the maximum current required by the following sys- tem is 2a. then, the maximum switching transition period is calculated using the following formula: t vc ii t f aa s sw max bat max in system inrush load sw max () () () = () () - = () m () - =m () 10 100 62 250 multiplying 3 by 250 m s gives 0.75ms, the minimum fault delay time. make sure this delay time does not fall outside of the safe operating area of the mosfet switch dissipat- ing 30w (6a ? 10v/2). using this delay time the c timer can be calculated using the following formula: cms a v pf itmer = m ? ? ? ? = 075 6 116 3879 . . therefore, c timer can be 3900pf. applicatio s i for atio wu u u
LTC1473L 11 v gg regulator inductor and capacitors the v gg regulator provides a power supply voltage signifi- cantly higher than either of the two main power source voltages to allow the control of n-channel mosfet switches. this micropower, step-up voltage regulator is powered by the higher potential available from the two main power sources for maximum regulator efficiency. applicatio s i for atio wu u u three external components are required by the v gg regu- lator: l1, c1 and c2, as shown in figure 5. l1 is a small, low current, 1mh surface mount inductor. c1 provides filtering to the input of the 1mh switched induc- tor and should be at least 1 m f to filter switching transients. the v gg output capacitor, c2, provides storage and filter- ing for the v gg output and should be at least 1 m f and rated for 25v operation. c1 and c2 can be ceramic capacitors. figure 5. v gg step-up switching regulator bat1 dcin v gg switching regulator v + sw gnd 1473 f05 v gg l1* 1mh c1 1 f 25v c2 1 f 25v to gate drivers (8.5v + v + ) LTC1473L *coilcraft 1812ls-105 xkbc. (708) 639-6400
LTC1473L 12 LTC1473L with battery charger typical applicatio s u in1 in2 diode timer v + v gg sw gnd 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 ga1 sab1 gb1 sense + sense ga2 sab2 gb2 LTC1473L c out r sense 0.04 w 1 m f 1mh si9926dy bat54c 100ma d1 mbrs130lt3 1473 ta03 dcin 3.3v bat1 4 nimh 3.3v or v bat1 c timer 2000pf c1 22 m f 25v r1 47.55k l1b* l1a* c2** 22 m f r4 24 w c3 22 m f 25v c4 0.22 m f l1a, l1b are two 33 h windings on a single inductor: coiltronics ctx33-3 tokin ceramic 1e22zy5u-c203-f c5 0.1 m f sync and/or shdn * ** si9926dy 1 m f + r2 12.45k r5 1k r3 1 w v sw v in fb s/s i fb v c gnd lt 1512 gnd logic driven
LTC1473L 13 2-cell li-ion to 5v/3.5a dc/dc converter with battery charger and automatic switchover between battery and dcin typical applicatio s u r sense 0.015 w m1 si4412dy c4 0.1 m f d1 cmdsh-3 c3 4.7 m f 16v d2 mbrs140t3 c in 22 m f 30v os-con c out 100 m f 10v 3 v out 5v/3.5a m2 si4412dy + + r1 105k 1% l1* 10 m h sgnd 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 c1 100pf c5 1000pf c ss , 0.1 m f c c2 , 220pf c osc 51pf r c , 33k c c 470pf + c6 100pf c2, 0.1 m f r2 20k 1% 2600pf c timer c7 1 m f c8 1 m f gnd sw boost gnd gnd uv gnd ovp clp cln comp1 sense gnd gnd v cc1 v cc2 v cc3 prog v c uvout gnd comp2 bat spin lt1511 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 dcin out a v in + a in b out b v + ref hyst ltc1442 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 1 2 3 4 8 7 6 5 74c00 12 3 4 5 6 13 12 11 14 bat54c d5 mbrd340 c11 0.47 m f d6 mbr0540t d4 mbrd340 l3*** 20 m h 2,3 1,4 c10 1 m f r13 5.1k 1% r12 3k 1% c16 220pf r sense 0.033 w r20 395k 0.1% r21 164k 0.1% c17 10 m f 8.4v li-ion battery r19 200 w 1% r15 1k c15 0.33 m f r16 300 w c14 1 m f r17 4.93k c12 10 m f c13 10 m f r sense 0.033 w r14 510 w r6 900k 1% r7 130k 1% r9 113k 1% r8 427k 1% r10 50k 1% r11 1132k 1% c9 0.1 m f r5 500k 7 l2** 1mh r18, 200 w, 1% 1473 ta04 *sumida cdrh125-10 **coilcraft 1812ls-105xkbc ***coiltronics ctx20-4 10 9 8 si9926dy r sense 0.033 w in1 in2 diode timer v + v gg sw gnd ga1 sab1 gb1 sense + sense ga2 sab2 gb2 LTC1473L si9926dy d3 6.8v tg boost sw v in intv cc bg pgnd extv cc c osc run/ss i th sfb sgnd v osense sense sense + ltc1735 8 + 5v
LTC1473L 14 typical applicatio s u automatic powerpath switching for 3.3v applications 3.3v or 5v, 6a, powerpath switch in1 in2 diode timer v + v gg sw gnd 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 ga1 sab1 gb1 sense + sense ga2 sab2 gb2 LTC1473L c out r sense 0.04 w 1 m f 1mh* si4966dy bat54c 1473 ta05 dcin 3.3v ltc1442 r1 1.65m 1% bat1 4 nimh 3.3v or v bat1 c timer 4700pf si4966dy 1 m f 1.182v 2 8 4 5 6 3 1 7 + + + r2 1.13m 1% * coilcraft 18126s-105xkbc in1 in2 diode timer v + v gg sw gnd 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 ga1 sab1 gb1 sense + sense ga2 sab2 gb2 LTC1473L c out r sense 0.015 w 1 m f 1mh si4966dy bat54c 1473 ta06 dcin 3.3v dcin 5v 3.3v or 5v 6a c timer 550pf si4966dy 1 m f + logic driven
LTC1473L 15 typical applicatio s u gn package 16-lead plastic ssop (narrow 0.150) (ltc dwg # 05-08-1641) protected hot swap tm switchover between two supplies for portable pc package descriptio u dimensions in inches (millimeters) unless otherwise noted. hot swap is a trademark of linear technology corporation 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 in1 in2 diode timer v + v gg sw gnd ga1 sab1 gb1 sense + sense ga2 sab2 gb2 LTC1473L l1*, 1mh c5 1 f c7 1 f 100k 100k c6 4700pf supply v2 3.3v supply v1 5v d1 mmbd2838lt1 q1 si9926dy q2 si9926dy r3 0.1 out 5v docking connector on long pin long pin short pin *1812ls-105xkbc, coilcraft 1473 ?ta07 gn16 (ssop) 1098 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 12 3 4 5 6 7 8 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.189 ?0.196* (4.801 ?4.978) 12 11 10 9 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.007 ?0.0098 (0.178 ?0.249) 0.053 ?0.068 (1.351 ?1.727) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.0098 (0.102 ?0.249) 0.0250 (0.635) bsc 0.009 (0.229) ref information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC1473L 16 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com ? linear technology corporation 1999 1473lf lt/tp 1099 4k ? printed in usa related parts typical applicatio u protected automatic switchover between two supplies part number description comments ltc1155 dual high side micropower mosfet driver internal charge pump requires no external components ltc1161 quad protected high side mosfet driver rugged, designed for harsh environment ltc1735 single high efficiency synchronous dc/dc controller constant frequency, 3.5 v in 36v, fault protection ltc1473 dual powerpath switch driver v + range from 4.75v to 30v ltc1479 powerpath controller for dual battery systems designed to interface with a power management m p lt1505 synchronous battery charger with adapter current limit high efficiency, up to 8a charge current, end-of-charge flag, 28-pin ssop, 0.5v dropout voltage lt1510 constant-voltage/constant-current battery charger up to 1.5a charge current for lithium-ion, nicd and nimh batteries lt1511 3a constant-voltage/constant-current battery charger high efficiency, minimal external components to fast charge lithium, nimh and nicd batteries ltc1558/ltc1559 backup battery controller with programmable output power supply backup using a single nicd cell ltc1622 current mode step-down dc/dc converter 550khz operation, 100% duty cycle, v in from 2v to 10v ltc1628 dual high efficiency synchronous buck dc/dc controller 2-phase switching, 5v standby in shutdown, fault protection lt1769 2a constant-voltage/constant-current battery charger charges lithium, nicd and nimh batteries, 28-lead ssop 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 in1 in2 diode timer v + v gg sw gnd ga1 sab1 gb1 sense + sense ga2 sab2 gb2 LTC1473L l1*, 1mh c5 1 f c7 1 f c6 2600pf + 5 6 7 + 3 2 1 8 4 1m 1m 10k 10k 1m supply v2 supply v1 1m 1 f 5v 18 3 lt1121-5 bat54c q1 si9926dy q2 si9926dy r3 0.033 out *1812ls-105xkbc, coilcraft 1473 ?ta02 lt1490

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